Minisymposium

Quantum computing has rapidly evolved in recent years, with platforms ranging from superconducting qubits and trapped ions to photonic and neutral atom systems. These diverse approaches offer unique strengths and challenges, driving the need for reliable methods to assess and optimize device performance. However, characterizing and benchmarking these quantum processors is challenging, particularly because the quantum state space grows exponentially with system size, making standard methods impractical. In this talk, I will introduce randomized measurements, a feasible solution that leverages random measurement bases to extract essential classical information from complex quantum states. This efficient conversion of quantum data enables deeper insights into quantum dynamics and to improve device calibration. Moreover, it integrates seamlessly with classical HPC and machine learning workflows, harnessing the resulting classical data. In this context, I will present RandomMeas.jl, an open-source Julia package that simplifies and standardizes the application of these measurement techniques. By equipping researchers with accessible tools for advanced quantum state characterization, this aims to foster broader adoption and innovation across the quantum computing community.

Although modern optical communications typically rely on digital signals, analog photonics has been an active field of research over the last decades. In parallel, photonics for computing experienced an intermittent research interest. Recent breakthroughs in artificial intelligence have sparked attention in novel computational frameworks, reigniting interest in analog photonic computing.This talk explores the potential of integrated photonics to realize analog photonic accelerators, in particular for machine learning applications. Various integrated photonic devices and system architectures are analyzed, exploiting wavelength division multiplexing for weight banks, coherent photonic crossbar arrays, and photonic-electronic multiply-accumulate neurons. Each architecture offers different advantages and trade-offs in terms of speed, resolution, power consumption, and footprint.Focusing on the latter architecture, different photonic integration technologies, including silicon-on-insulator, lithium niobate-on-insulator, and indium phosphide, are reviewed, the results of experimental implementations and the outstanding challenges are discussed, showcasing future prospects in the field of high-speed neuromorphic photonics.

The need to repeatedly shuttle around synaptic weight values from memory to processing units has been a key source of energy inefficiency associated with hardware implementation of artificial neural networks. Analog in-memory computing (AIMC) with spatially instantiated synaptic weights holds high promise to overcome this challenge, by performing matrix-vector multiplications directly within the network weights stored on a chip to execute an inference workload. In this talk, I will first present our latest multi-core AIMC chip in 14-nm complementary metal–oxide–semiconductor (CMOS) technology with backend-integrated phase-change memory (PCM). The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network. Experimental inference results on ResNet and LSTM networks will be presented, with all the computations associated with the weight layers and the activation functions implemented on-chip. Then, I will present our open-source toolkit (https://aihw-composer.draco.res.ibm.com/) to simulate inference and training of neural networks with AIMC. Finally, I will present our latest architectural solutions to increase the weight capacity of AIMC chips towards supporting large-language models, as well as alternative solutions suited for low-power edge computing applications.

This panel will explore emerging computing technologies that are shaping the future of high-performance computing (HPC), including advances in architectures, accelerators, and software ecosystems. Experts from academia and industry will discuss the opportunities and challenges in scaling next-generation HPC systems to meet the growing demands of scientific discovery, AI, and data-intensive applications.